(1) Field of the Invention
The invention relates to processes for the manufacture of semiconductor devices and more particularly to processes for forming ultra thin gate oxides for self-aligned gate field effect transistors.
(2) Description of Prior Art and Background to the Invention
Complimentary metal oxide semiconductors(CMOS) field effect transistor(FET) technology involves the formation n-channel FETs(NMOS) and p-channel FETs(PMOS) in combination to form low current, high performance integrated circuits. The complimentary use of NMOS and PMOS devices, typically in the form of a basic inverter device, allows a considerable increase of circuit density of circuit elements by reduction of heat generation. The increase in device density accompanied by the shrinkage of device size has resulted in improved circuit performance and reliability as well as reduced cost. For these reasons CMOS integrated circuits have found widespread use, particularly in digital applications.
The basic MOSFET, whether it be NMOS or PMOS is typically formed by a self-aligned polysilicon gate process. An region of active silicon region surface for the device is defined on a silicon wafer by an opening surrounded by field oxide isolation(FOX). A gate oxide is then grown on the exposed silicon regions and a polysilicon gate electrode is patterned over the gate oxide. Source and drain regions are next formed in the active region, typically by ion implantation. The device is completed by depositing an insulative layer over the wafer and forming contacts to the source/drain regions and to the gate electrode through openings in the insulative layer.
The performance of the MOSFET is inversely proportional to the gate oxide thickness. Efforts to enhance performance as well as reduce power consumption have driven gate oxide thicknesses to well below 100 Angstroms. It was originally predicted that the physical limit of gate oxide thickness is somewhere around 30 Å because below this thickness carriers are removed by direct tunneling, faster than they can be supplied by thermal generation (Wolf, S., “Silicon Processing for the VLSI Era”, Vol.3, Lattice Press, Sunset Beach, Calif., (1995), p438). However, recent studies by Bell Laboratories scientists now predict that the physical limit is of the order of 5 atoms which translates to about 14 Å for an SiO2 dielectric.
MOSFET devices are currently being developed which have gate oxide thicknesses as low as 20 Å. As one might expect, serious new problems arise when the technology is driven to such levels requiring the invention of new methods to deal with them. Although some of these problems may not be generally soluble with today's technology, it is prudent to selectively exploit situations where the effects of these problems are minimal.
A problem with this procedure is that a thin layer of native oxide forms on the silicon surface during a non-HF stripping and cleaning processes which remove the photoresist. Native oxide grows quickly and a roughly 10 Angstrom thick layer is formed in the order of minutes and reaches a final thickness of about 30 Angstroms in about a day at room temperature. The native oxide is of poor structural quality and readily absorbs contaminants. Mobile oxide contaminants are known to segregate at the silicon/oxide interface. If the native oxide is left in place during gate oxidation, it's contaminants and structural defects will be incorporated in the gate oxide. If left in place during the formation of a 20 Å thin gate oxide by thermal oxidation, the 10 Å or so of poor quality native oxide would comprise about half of the total. Obviously, a gate insulator with such a large poor quality portion would show degraded performance of the MOSFET. It would therefore be desirable to have a method for reducing native oxide formation on nascent silicon surfaces, as much as possible. The present invention provides a method for providing a clean chemically grown oxide of high quality on the freshly exposed silicon surface during the cleaning process. The oxide is grown by introducing by ozone in the cleaning process. This high quality oxide passivates the silicon surface against subsequent native oxide growth and becomes the base for the subsequently formed gate oxide.
The RCA process, which uses NH4OH/H2O2 and HCL/H2O2 solutions to clean particulates and other chemical residues from silicon wafers, was first introduced in 1970 by Keen and Poutinen at RCA and is well known in the art. Since it's introduction many variations of the process have been developed. Details of this procedure may be found in Wolf, S. and Tauber, R. N., “Silicon Processing for the VLSI Era”, Vol.1, Lattice Press, Sunset Beach, Calif., (1986), p.516.
In the RCA process The first ammoniacal peroxide solution (SC-1), when used in concert with the application of ultrasonic or megasonic agitation, is effective for removing organic residues and particulates while the second acidic peroxide solution (SC-2) is effective for removing metallic contaminants. The abbreviations SC-1 and SC-2 are commonly used and refer to standard clean 1 and 2 of the RCA process. A dilute HF treatment is often added between SC-1 and SC-2 to remove silicon oxide.
Matthews, U.S. Pat. No. 5,464,480, U.S. Pat. No. 5,727,578, and U.S. Pat. No. 5,911,837 show an apparatus and a version of the RCA cleaning process wherein ozone is used in place of the peroxide in the SC-1 and SC-2 solutions and in water rinses to provide active oxygen for the removal organic contaminants such as photoresist residues.